MRF Timing System Hardware and Firmware Reference

Introduction:

• The MRF Timing System
• Examples of usage scenarios

Reference Manual:

• Event Master
• Fanout and Concentrator
• Event Generator
  • Event Generation
  • Distributed Bus
  • Timestamping support
  • Configurable Size Data Buffer
  • Programmable Outputs
  • Utility Functions in the Event Generator
  • Front Panel TTL Input with Phase Monitoring
  • Event Clock RF Source
• Delay Compensation
  • Topology ID
  • Active Delay Compensation
• EVG Function Register Map
  • Register descriptions
  • Front Panel Input Phase Monitoring Registers
  • Embedded Event Receivers
  • FCT Function Register Map
• MTCA-EVM-300
  • TTL Input Levels
  • mTCA-EVM-300 mTCA.4 Backplane Trigger Bus Lines
  • mTCA-EVM-300 mTCA.4 Rear Transition Module Signals
  • Register Mapping
• VME-EVM-300
  • TTL Input Levels
  • VME-EVM-300 VME P2 User I/O Pin Configuration
  • VME-EVM-300 CR/CSR Support
  • Function 0 and 1 Registers
  • Function 2 Registers
• EVM Firmware Version Change Log
  • mTCA.4 development branch
  • Merging of VME and mTCA.4 development branches
• FCT Function Register Map
  • Status Register
  • Control Register
• Event Receiver
  • Functional Description
  • Event Decoding
  • Heartbeat Monitor
  • Event FIFO and Timestamp Events
  • Event Log
  • Distributed Bus and Data Transmission
  • Pulse Generators
  • Prescalers
  • Programmable Front Panel, Universal I/O and Backplane Connections
  • Flip-flop Outputs (from FW version 0E0207)
  • Front Panel Universal I/O Slots
  • VME-EVR-300 GTX Front Panel Outputs and mTCA-EVR TCLKA/TCLKB Clocks
  • mTCA-EVR-300RF GTX Outputs
  • GTX Pulse Mode
  • GTX Frequency Mode
  • GTX Pattern Mode
  • GTX GUN-RC-300 Mode (mTCA-EVR-300RF)
  • GUN-RC-300 Pulse Mode
  • GUN-RC-300 Pattern Mode
  • Configurable Size Data Buffer (EVR)
  • Segmented Data Buffer
  • Interrupt Generation
  • External Event Input
  • Programmable Reference Clock
  • Fractional Synthesiser
• MTCA-EVR-300
• VME-EVR-300
  • VME-EVR-300 Front Panel Connections
• PCIe-EVR-300DC and IFB-300 Connections
• PCIe-EVR-300DCS and IFB-300S Connections
• Event Receiver Registermap
  • Register Map
  • Status Register
  • Control Register
  • Interrupt Flag Register
  • Interrupt Enable Register
  • Hardware Interrupt Mapping Register
  • Software Event Register
  • PCI Interrupt Enable Register
  • Receive Data Buffer Control and Status Register
  • FPGA Firmware Version Register
  • Clock Control Register
  • GPIO Pin Direction Register
  • SPI Configuration Flash Registers
  • Delay Compensation Status Register
  • Sequence RAM Control Register
  • Prescaler Pulse Trigger Registers
  • Distributed Bus Pulse Trigger Registers
  • Pulse Generator Registers
  • Input Mapping Registers
  • GTX Output Control Register
  • Data Buffer Segment Interrupt Enable Register
  • Data Buffer Checksum Flag Register
  • Data Buffer Receive Flag Register
  • SFP Module EEPROM and Diagnostics
  • Hardware Configuration Summary
  • PCIe-EVR-300DC and IFB-300 Connections
  • mTCA-EVR-300 Connections
  • PCIe-EVR-300DC Firmware Upgrade
• EVR Firmware Version Change Log